The present invention relates to a method and apparatus for handling information sent through a digital network and, more specifically, to the segmentation and reassembly of data frames within an ATM network.
Asynchronous Transfer Mode (ATM) or xe2x80x9ccell switchingxe2x80x9d is a method of transmitting digital information wherein the information is broken into equal sized units called cells. The individual cells of information are transmitted from a source node to a destination node through a pathway (or connection) through a digital network. The digital network may be constructed of digital switches coupled together by digital communication links which carry the cells of information between the digital switches along the connection. The digital switches route the cells from incoming communication links to outgoing communication links and finally to the destination node.
Before any information can be transported through the network as ATM cells, the information must be segmented into cells. Typically, this is accomplished by segmentation and reassembly (SAR) engines which are used to xe2x80x9cchop upxe2x80x9d user data (typically formatted as variable length frames) into fixed length cells for transmission. As the data frames are segmented, ATM header information is added to each cell and the cells are transmitted into the ATM network. During reception, the header information is stripped from the cells and the remaining fixed length payloads are reassembled into variable length data frames for use by appropriate user applications. Typically, the payload information for each cell is copied into memory as it is received during the reassembly process.
In ATM networks the segmentation and reassembly (SAR) functions are performed at the interface between an ATM layer and an ATM adaptation layer (AAL). During transmission, higher level services pass user data to the AAL where, first, a convergence sublayer forms convergence layer protocol data units (CS-PDUs). These CS-PDUs will, generally, be larger than the payload capacity of an ATM cell. Therefore, a second sublayer, the segmentation and reassembly (SAR) sublayer, accepts the variable length CS-PDUs and fragments them into appropriate payloads (48-bytes) for transmission. These payloads are referred to as segmentation and reassembly protocol data units (SAR-PDUs) and are passed to lower layers in the ATM protocol model for further processing. During reception, a reverse operation takes place and the SAR sublayer is responsible for reassembling messages as they are received.
Several ATM AALs have been developed for various applications. AAL Type 5 (AAL-5) was designed for variable bit rate, connection-oriented or connectionless services and provides good error detection/correction capabilities and high line efficiency. The AAL-5 methodologies are illustrated in FIG. 1. During transmission, a user message 10 is passed from higher level protocols to the AAL, where it is referred to as an AAL Service Data Unit (AAL-SDU) 12. As shown in FIG. 1, the AAL-5 convergence sublayer uses the AAL-SDU 12 to create variable length protocol data units (CS-PDUs) 14. The CS-PDUs are made up of various fields. The User Data Field 16 comprises data from the higher layer protocols and may be up to 65,535 bytes in length. The Pad field 18 is used to align the entire CS-PDU 14 on a 48-byte boundary (i.e., the entire CS-PDU 14 is a multiple of 48-bytes in length). The Control field 20 is two bytes in length and is presently reserved for future use. The Length field 22 indicates the actual length of the User Data Field 16 and is two bytes long. The CRC-32 field 24 is appended to provide error detection in the CS-PDU 14.
CS-PDUs are passed to the AAL-5 SAR sublayer. The SAR sublayer fragments the CS-PDUs to fixed-length SAR-PDUs 26, each 48-bytes long. There are no new headers or trailers added by the SAR sublayer in AAL-5. No padding is necessary because the CS-PDU 14 was padded to a multiple of 48-bytes. As further shown in FIG. 1, the SAR-PDU 26 is passed to the ATM layer where a 5-byte header 28 is added to form an ATM cell 30. During reception, these operations are performed in a reverse order to rebuild the user message 10.
It is an object of the invention to provide means for cell segmentation and reassembly in a digital switch.
In one embodiment, a method of reassembling frames within a switch of a digital network is provided. A plurality of cells are received at the switch and stored in a logical queue. The cells contain data information and logical connection information and the logical queue corresponds to the logical connection identified by the logical connection information. The cells are combined into a frame by extracting the cells from the logical queue and storing the cells to a local memory so that the data information is preserved. The cell extraction may be accomplished by identifying a last cell of the plurality of cells, the last cell indicating an end of the frame, and then identifying a frame length for the frame. The frame length may be provided to a local processor and the data information of the cells transferred to a number of memory locations in a local memory at the direction of the local processor, the number of memory locations being based on the frame length. The memory locations may be contiguous and the transfer may be accomplished using a DMA engine. During the transfer, error detection operations, such as computing a CRC-32 value for the data information during and comparing the computed CRC-32 value with a received CRC-32 value for the frame, may be performed.
In a further embodiment, a method of transmitting information in a digital network is provided. The method includes segmenting a data frame into a plurality of cells and injecting each of the cells into a logical queue associated with a connection for the frame in a digital network. The step of injecting may include transferring each of the cells to a number of memory locations within a cell memory; and establishing a series of linked list pointers associated with the memory locations, the series of linked list pointers comprising the queue. The cells may then be transmitted into the digital network in an order consistent with the linked list pointers.
In yet another embodiment, a digital switch is provided. The digital switch may include a queuing circuit configured to store a plurality of ATM cells comprising a frame. The cells include payload information and logical connection information and are organized into a logical queue based upon the logical connection information. The switch may further include a reassembly engine configured to detect a last cell of the frame, to notify a local processor of the switch when the last cell is detected, to receive an extraction request from the local processor in response to the notification, and to extract the cells from the memory so as to preserve the payload information. The reassembly engine may further be configured to strip off the logical connection information from the cells while extracting the cells from memory. In addition, the reassembly engine may perform error detection operations for the frame using the payload information while extracting the cells. For example, the reassembly engine may compute a CRC-32 value for use in the error detection operations.